HPC on RISC-V: a hot topic at the 2024 International Supercomputing Conference

The International Supercomputing Conference (ISC) attracts almost 4,000 attendees and is the largest high performance computing (HPC) conference in Europe. Taking place in May in sunny Hamburg, this year attendees were treated to a five-day programme packed with new technology, exciting talks and thought-provoking discussions. 

HPC Next: the RISC-V Ecosystem

Firstly, the HPC SIG (special interest group) hosted an hour-long Birds of a Feather (BoF) session on RISC-V. BoFs explore a specific topic with the audience, combining a two-way discussion on the concerns and challenges of the audience with the experience of the panel. This allows the panel to explore different ideas and gauge reactions. Many in the audience would not have used RISC-V technology before – and are simply interested in learning more and challenging their preconceptions. 

In the anticipation that this would prove popular, the organisers hosted us in the largest hall available to BoFs, which ultimately proved justified as we filled the place with standing room only!

The session, which I chaired, involved panellists Teresa Cervero from BSC, Oliver Perks from Rivos, Andrew Richards from Codeplay and Daniele Gregori from E4 Computer Engineering. After a short introduction by each panellist we dove straight into the interactive session, using Mentimeter to enable anonymous questions and voting on topics. 

One of the most interesting outcomes resulted from asking the audience to vote on the aspect of RISC-V they felt was most important for HPC. The results are illustrated below.

ISC participants represent a broad cross-section of the HPC industry, from hardware manufacturers and supercomputing centres to end-users. It surprised us that the HPC community valued the open nature of RISC-V as its most important feature as we expected participants to be driven by more operational concerns such as performance and power efficiency, which came second. 

However, the HPC community has a long history of embracing and establishing open standards, both in hardware and software so maybe this is not so surprising. These software standards, such as MPI and OpenMP, have ensured software portability between systems for decades and therefore the community can already see the benefit of openness. 

Q&A

During the Q&A we discussed a full range of topics concerning RISC-V, from ISA specification to software development and community.

On the hardware side it was asked whether RISC-V will enable application specific hardware specialisation. The panel discussed this at length, with the point being made that whilst RISC-V enables flexibility in the implementation, vendors must still adhere to market forces. Vendors are free to make a variety of different choices that then suit their customer base, however there must be a financial justification. 

The commercial and community aspects of RISC-V were also discussed. Audience members asked how commercial companies can be encouraged to adopt RISC-V, and another attendee asked whether there needs to be a single company driving the standard. The panel discussed the large number of companies already invested in RISC-V, developing both hardware and software solutions based upon the standard, and how RISC-V International is the organisation that drives all of this forward and connects the community together.

On the software side we discussed activities around developing and optimising the software building blocks for HPC: the libraries and tools required by users and supercomputing centres. The panel was able to highlight several activities such as recent work enhancing BLAS libraries to take advantage of RISC-V vectorisation, and discuss initiatives such as RISE which, amongst other things, have recently released a RISC-V software development optimisation guide (see link below).

The HPC SIG is currently undertaking a gap analysis of RISC-V in HPC to understand, across the community, what is being done and what needs to be prioritised. It was also queried whether lessons can be learned from the relatively recent porting of HPC software to the Arm architecture, with the panel sharing that whilst there is still specialist work needed, especially to optimise for RISC-V, this previous work has led to both specific code-level improvements and also lessons learned by the community that make this task much easier.

The level of interest shown in RISC-V by the HPC community was very encouraging to see. There is clearly an appetite for hardware, and a willingness to contribute to the software ecosystem.

The RISC-V for HPC workshop

On the last day of the conference, ISC hosts a day dedicated to workshops. Each can be thought of as a mini-conference, with their own set of speakers and research papers. We had a half-day workshop at ISC exploring RISC-V for HPC, and this built upon very successful and popular workshops last year at both SC and ISC. (See link below to download presentations from the workshop.)

Talks

A keynote was given by Carlos Puchol, who leads the EUPilot project which is using RISC-V to develop accelerators as part of the European Processor Initiative (EPI). This project involves numerous European partners, from both academia and vendors, to develop RISC-V hardware solutions and further enhance the software ecosystem. The workshop included five research papers, which covered a range of topics including benchmarking RISC-V CPUs, further developing the software ecosystem, and machine learning on RISC-V.

Additionally we wanted to give the audience a view of some of the more mature aspects of the ecosystem. Consequently, Oliver Perks gave a talk on the RISE initiative, demonstrating to the audience that this is a serious undertaking with big players investing in the RISC-V software ecosystem. 

Volker Politz from Semidynamics, Karel Masařík from Codasip, and Daniele Gregori from E4 Computer Engineering each gave talks about their hardware products and their views on the role of RISC-V in HPC. Not only did this demonstrate that there is real hardware and IP available that people can buy and leverage for their workloads, but furthermore it was interesting to hear the opinions that drive some of the commercial decisions. An interesting discussion was held, for instance, around the difference between an open ISA standard and an open microarchitecture. It was interesting to see that there was some misunderstanding in the wider HPC community around the separation between the two, and the fact that a healthy and vibrant commercial hardware ecosystem can co-exist with an open ISA. This is potentially where we need to consider some education, as clearly not all of the wide range of HPC community members necessarily understand the differences between these two concepts.

RISC-V on the show floor

Whilst we may be a few years from mainstream RISC-V adoption in HPC, we are starting to see a few examples of real hardware based on the RISC-V ISA. Some of these were visible on the show floor where attendees were able to demo them.

For example, BSC showcased the RISC-V-based VEC chip, which is part of the EPI project under the EPAC accelerator. Whilst there is still on-going development work around VEC, BSC allowed users to have an early glimpse of the technology by seeing hands-on demos running on the chip. Tenstorrent was also present with a booth in the exhibition, demoing their RISC-V-based AI accelerators.

Next: RISC-V at SC24

The ISC workshop was a great success, with the number of attendees suggesting RISC-V will be a major force in HPC very soon. If you missed this event, the good news is we will be doing it again at Supercomputing (SC24) in Atlanta, where we will host another workshop on RISC-V for HPC on the afternoon of Monday 18th November. 

For this workshop we are trialling two research paper submission dates, to help give those who require visas a bit more time. The early submission date is the 1st of July, and the main submission deadline is the 9th of August. For more details, see:
https://riscv.epcc.ed.ac.uk/community/workshops/sc24-workshop

Links

RISC-V software development optimisation guide:
https://gitlab.com/riseproject/riscv-optimization-guide 

RISC-V for HPC workshop presentations:
https://riscv.epcc.ed.ac.uk/community/workshops/isc24-workshop/

^{This article was first published at https://riscv.org/blog.}